1. Field of the Invention
The invention relates to a method for increasing the cut-off frequency of flip-flops.
2. Description of the Related Technology
Circuits with flip-flops are used in the digital signal processing field for storing logic states. They consist internally of a control element, which takes the logic state which is applied to its input and makes it available for evaluation at its output, and of a holding element, which maintains the state which is set. Using a clock, inter alia, so-called frequency dividers or dividing stages can be assembled from a series connection of a plurality of flip-flops. The processing of increasingly higher frequencies requires dividing stages which operate at several gigahertz, especially in the GSM, ISM wireless communication field. Because of the development to higher frequencies, the transistors which are used in the flip-flops have to meet higher requirements in terms of the cut-off frequency thereof, which must be approximately twice the maximum frequency of the divider.
The transistor production process is becoming significantly more complex and cost-intensive due to the higher frequency requirements. The cut-off frequency of an individual flip-flop circuit results from the signal propagation time within the circuit. It is essentially determined by the product of the load resistance and the capacitance at the output line of the flip-flop and, considered quite generally, can be conceived as a low pass filter. With a given load resistance, the transistors of the circuit must be able to handle a sufficiently high current, according to the value of the capacitance which is to be recharged upon a change occurring in the logic state. If this is not the case, high-current effects will occur and the cut-off frequency of the flip-flop will drop drastically.
In the methods known from the prior art, for example in M. Wurzer et al., ISSCC 2000, San Francisco, the transistors which are used in the control elements and holding elements are dimensioned to prevent high-current effects following the maximum peak current values occurring in the control elements.
The disadvantage of the previous conventional method and circuit design lies in the fact that the different electrical requirements to be met by the control element and the holding element are not taken into account, and the transistor capacitances linked with the area are consequently not optimized. As these have to be recharged at the output lines of the flip-flop each time there is a change in the logic state, this has an adverse influence on the cut-off frequency of the flip-flop.
The present invention seeks to provide a method which increases the cut-off frequency of flip-flops and which can at the same time be implemented easily and inexpensively.
According to a first aspect, the present invention provides a method for increasing the cut-off frequency of a flip-flop including at least one control element having at least two transistors and at least one holding element having at least two transistors, said control element setting, by means of a first current, a logic state of said flip-flop, said logic state being maintained by said holding element by means of a second current, wherein the current carrying capacity of said transistors of said control element is adapted to the value of said first current, and the current carrying capacity of said transistors of said holding element is adapted to the value of said second current.
According to a second aspect, the present invention provides a flip-flop including at least one control element having at least two transistors and at least one holding element having at least two transistors, and means supplying a first current to said control element so that it sets a logic state of the flip-flop and a second current to said holding element so that it maintains said logic state, wherein said transistors of said holding element have smaller dimensions than said transistors of said control element.